Help: Counter / Master Clock Behavior
I’m sure this has been discussed but I couldn’t find it. Is the counter module behaving as intended? As expected?
Its behavior compared to the master clock make it quite difficult to use for at least some use cases.
The master clock’s default value when the transport isn’t running seems to be an instant before 0. You can see this if you hook up a cv sequencer to the master clock as it selects the last step.
The counter module’s default value is 0. You can see this by hooking up a cv module to the counter and see that the first step is selected.
If a counter is hooked up to the master clock this is their initial positions when transport is stopped.
As soon as the transport starts the clock increments/wraps around to 0, the first step pulsing the counter causing it to immediately advance to the second step. The main clock and the counter are now one step out of phase. This could be fixed with an intermediate sequencer or shaper.
When the transport is stopped the clock resets to it’s “-1” value. The counter’s value, however, retains its current position and starts from where it left off (well from the next step anyway).
At this point anything controlled by a counter is completely out-of-sync with the main clock.
It doesn’t seem like there’s anything other than a trigger button to hook the counter’s reset to to keep them in sync.
Youtube: https://youtu.be/xPv1djLComw Patch storage: https://patchstorage.com/counterbehavior/
Comments
Can’t seem to edit the original post so I’ll add that I’m seeing the same behavior of memory when a cv sequencer is getting its clock from another cv sequencer. Even if the first cv sequencer tied to the master clock resets when transport stops the downstream cv sequencer doesn’t.